Please Log in (Forgot) or Register boundary scan jtag test
JTAG programming software
Boundary Scan JTAG

» Scan Exec Brochure

» Eclipse Family Overview » Test Development
» Manufacturing Test
» Diagnostics and Repair

Standard Features:

» Test Execution
» Test Flow Control
» Diagnostics
» Debug
» Data Logging
Schematic Debugger
Physical Debugger

Optional Capabilities:

» Advanced Diagnostics
» C++ and Libraries
» Network Licensing

Hardware Options:

» UltraTAP
» PCI ScanLab
» Parallel Port

Scan ExecutiveTM Lowers the Cost and Reduces the Complexity of Manufacturing Test

Scan Executive executes device configuration and manufacturing test suites developed with the EclipseTM Test Development Environment. Scan Executive leverages cost-effective test application hardware such as PCI Scan LabTM, or RCT IITM (Reduced Contact Tester) and UltraTAPTM.

Typical Test Execution Process

Running Scan Executive is a simple process. Testing is executed using the graphical user interface. The Scan Executive GUI is very intuitive so manufacturing personnel with limited IEEE 1149.1 test expertise can successfully use Scan Executive.

Step 1 - Load Test

Scan Executive detects the presence of the test application hardware and loads a single Test file that contains links to all data and scripts that will be needed to run a test.

Step 2 - Start a Test

Scan Executive runs individual commands from the primary script in the Test file. Scan Executive's settings determine if the operator must supply the lot type and serial number before actual testing begins.

Step 3 - Apply Test Data to UUT

Scan Executive drives IEEE 1149.1 test data to the UUT. After each test completes the response from the UUT is captured and analyzed. Status from passing units is reported back in the Scan Executive Test Status Window and/or to other specified devices. Result data is also logged by lot type; serial number or from the DUT card ID for each UUT.

In the event of a failure, detailed diagnostics are provided and there is the option to debug the PCB using Schematic Logic ProbeTM or Visual Fault AnalyzerTM