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JTAG programming software
Boundary Scan JTAG

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Standard Features:

BSDL Library
Schematic Debug
» Visual Fault Analysis
» Timing Diagram
» TCL Scripting Language

Tests & Programming
Scan Path Test
Interconnect Pin Fault
Memory Test
» FLASH Programming
» ScanWorks®

Analog Instrument
VISA Instrument Control
GPIB IEEE 488 Control

1149.1/.6 Interconnect
Interconnect Diagnostics
Vector Translator
C++ and Libraries
LabView/TestStand VI
Network Licensing

WGL Vector Support
Simulation Interface

Hardware Options:

UltraTAP JTAG Controller
PT100Pro Production Tester
PT100 Multiport JTAG
RCT Benchtop Tester
Digilent HS2-JTAG
Intel/Altera ByteBlaster
Xilinx USB Cable II

» Eclipse Brochure

» Eclipse Family Overview
» Test Development
» Manufacturing Test
» Diagnostics and Repair

Boundary Scan JTAG Scan Path Diagnostics

Boundary Scan Diagnostics for scan path problems is completely automated in the Eclipse family of boundary-scan tools. A robust set of pin level diagnostic capabilities to enable manufacturing personnel to isolate and correct problems inadvertently introduced during the PCB assembly process. The Scan Executive Manufacturing Test Station is unique in the industry as it provides the same diagnostic capabilities found in the Eclipse Test Development Environment as standard features. Many 1149.1 tool vendors do not provide diagnostic capabilities in their standard product offerings and force users to purchase a separate package to diagnose failures. Not having adequate diagnostic capabilities during PCB test is more costly in terms of time-to-market and engineering opportunity costs, lost debugging and isolating faults. The Eclipse family provides advanced diagnostics for Scan Path faults, IC to IC interconnect test faults and IC to Memory device interconnect faults. All of the diagnostic engines provide compatible fault diagnostic messages to make it simple to understand the fault occuring.

Scan Path Diagnostics

The EclipseTM Scan Path Integrity Test (or SPIT) automatically verifies that all of a design's test logic is functioning properly. The Scan Path Integrity Test will return pin-level diagnostics for each type of boundary-scan chain failure so that the test logic can be debugged, repaired and the test process can continue.

Status Window Displaying a Fault During SPIT
- SPIT pinpoints the error between two devices on a board

PinFault Diagnostics

For each PCB level solder failure, Eclipse will display the PinFault Diagnostics list, which includes, the device name and pin where the failure was observed.

Status Window Displaying PinFaults

Boundary-Scan Intelligent Diagnostics (BSID)

Boundary-Scan Intellitigent Diagnostics (BSID) is an advanced form of diagnostics that uses the failure data generated by the Eclipse Board Interconnect Test ATPG engine to isolate the failing devices. This diagnostic engine is directly compatible with the diagnostic engine in the Scanexecutive runtime. Boundary-Scan advanced diagnostics for ScanExecutive- BSID

Status Window Displaying a Short Fault