XILINX SYSTEMACE FPGA CONFIGURATION PROM ALTERA SYSTEM CONFIGURATION

SystemBIST^TM is a vendor independent solution that configures any IEEE 1149.1 and IEEE 1523 complaint FPGA or CPLD regardless of what programmable logic vendor it comes from. The table below highlights the advantages of Intellitech's vendor independent SystemBIST solution over that of the Xilinx SystemAce offering.

Features	Comment	SystemBIST	System ACE CF	System ACE MPM	System ACE SC
Memory Density	SystemBIST has patent-pending configuration data re-use and compression that reduces amount of FLASH area. Current CompactFLASH storage media for SystemACE result in high cost premiums are paid for CF storage above 256MB	up to 2 Gbit	up to 8 Gbit	16 Mbit 32 Mbit 64 Mbit	16 Mbit 32 Mbit 64 Mbit
Production FLASH Programming	SystemBIST uses patent-pending FAC (Fast Access Controller) for high-speed FLASH programming through external Eclipse tool. Xilinx cable and speeds not suitable for production FLASH programming	on-board FLASH programming as fast as off-board	Separate CF programmer	Xilinx or 3rd party programmer	Xilinx or 3rd party programmer
Number of Components	Part Count varies with amount of FLASH and SystemBIST Targets	2-3	2	1	3
Shared Memory with CPU	FPGA configuration data and test images can be stored in the same FLASH as used by the CPU saving on parts, lowering cost of non-volatile memory needed for configuration and saving PCB area	Yes	No	No	No
Min board Space	1/2 of SystemBIST components can be mounted on back of PCB	9.6 cm²	25 cm²	12.25 cm²	custom
Cost per Mbit	SystemBIST w/128Mbit FLASH	$0.60-$.75	under $1	$1-3	$5-10
Compression	SystemBIST reduces test and configuration data	Yes	No	Yes	Yes
Configuration Data Re-use	SystemBIST also has patent-pending design data re-use unlike SystemACE. One 4Mbit FPGA design takes only 4Mbit regardless of how many instances occur in the PCB, system design or how many different design suites it exists in	Yes	No	No	No
Select Map Support	Xilinx Proprietary - extra design time needed on multi-vendor PCBs. While it is claimed SystemACE can program all the FPGAs across multiple PCBs, selectMAP cannot be used in that architecture	no	no	SelectMAP for up to 4 FPGAs	SelectMAP for up to 4 FPGAs
Slave Serial Support	Slave Serial is no faster than SystemBIST. Limited to 8 devices, SystemACE requires an ad-hoc design in order to address and configure FPGAs over a multi-slot, multi-PCB system	no	no	Slave Serial up to 8 FPGAs	Slave Serial up to 8 FPGAs
Uses IEEE 1149.1	Unlike SystemACE, SystemBIST drives the IEEE 1149.1 without adding its own boundary-register to the scan-chain	Yes	Yes	No	No
Configures all IEEE 1149.1 and IEEE 1532 devices	SystemBIST configures all IEEE 1532 and IEEE 1149.1 devices	Yes	Xilinx FPGA only	No	No
Maximum number of devices that can be configured		unlimited, any vendor	unlimited number of Xilinx FPGAs	4 Xilinx FPGAs in SelectMAP, 8 Xilinx FPGAs in serial	4 Xilinx FPGAs in SelectMAP, 8 Xilinx FPGAs in serial
Serial Configuration Speed	SystemBIST is just as fast when compared to Xilinx Serial Master/Slave mode. No specific advice is given from Xilinx on how to achieve 66Mbit performance on a PCB when the CCLK is distributed to 8 devices over a wide area	64Mbits/sec	16.7 Mbits/sec	Max of 66Mbit/Sec for up to 8 devices	Max of 66Mbit/Sec for up to 8 devices
Configuration Speed for 4 devices in selectmap mode	SelectMAP is faster if your PCB design supports the higher data rates however it is Xilinx specific. For multi-pcb designs, no help is given to achieve 152Mbit/sec over multiple PCBs and large distances. If more than 4 FPGAs are needed in the PCB design, a second SelectMAP controller is needed.	N/A	N/A	1mbit-152Mbit/sec	1mbit-152Mbit/sec
Maximum number of designs	SystemBIST enables 15 design suites, which can contain any number of FPGA designs	15 Design & Test Suites, 1 reset Suite	unlimited	8 Design Suites	8 Design Suites
FPGA configuration diagnostics	With SystemACE, If an FPGA fails to configure no indication is given as to which FPGA failed. The "Done" Pin needs to be examined to determine which FPGA failed configuration. Patent-Pending architecture of SystemBIST enables diagnostic codes for each FPGA configuration.	Per FPGA diagnostic code	Entire PCB Go/No-Go	Entire PCB Go/No-Go	Entire PCB Go/No-Go
FPGA configuration decision making/branching	SystemBIST is a processor which can make decisions, adjust TCK rates, display text messages	Yes	simple sequencer	simple sequencer	simple sequencer
Automatic Error Handling	The SystemBIST patent-pending architecture returns the PCB to a known safe state. Upon detecting a configuration or test failure, SystemBIST will automatically branch to 'reset' or customer supplied handling routine	Yes	NO	N/A	N/A
CPLD in-system re-configuration	SystemBIST enables in-the-field CPLD reconfiguration. A separate mechanism must be designed when using SystemACE	Yes	no	no	no
CPLD in-system re-configuration diagnostics	Separate diagnostic code for each CPLD that fails to configure	Per CPLD diagnostic code	N/A	N/A	N/A
On-board PCB test	SystemBIST will perform all 1149.1 based tests on board	Yes	No	No	No
On-board PCB test diagnostics	via 8 bit data bus or text messages via serial RS232 interface	Yes	No	No	No
On-board Failure Logging	SystemBIST logs failures to FLASH memory automatically for later retrieveal by a CPU or Eclipse boundary-scan test tools	Yes	No	No	No
Support for dynamic scan-chains	SystemBIST handles dynamic scan-chains introduced by 'linking' devices such as the Texas Instruments SPL, ASP, National Semiconductor Scan Bridge and Intellitech SRL	Yes	No	N/A	N/A
Non-Volatile Media		INTEL OR AMD	CompactFLASH	AMD FLASH	AMD FLASH
Non-Volatile Media Sharing	CPU boot FLASH can be used for test and configuration data	INTEL OR AMD	no	no	no

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Intellitech is a registered trademark and SystemBIST is a trademark of Intellitech Corp.
Xilinx and SystemACE are trademarks of Xilinx Inc.

Xilinx SystemACE vs. SystemBIST FPGA Configuration and embedded Test