Boundary-Scan 1149.1 Test
Eclipse provides design engineers with several utilities to debug their design and test programs. Designers can use Eclipse to single step through individual test patterns and have the choice of viewing the resultant data using a spreadsheet window or with the Eclipse Timing Diagram Analyzer. The Eclipse Timing Diagram Analyzer provides capabilities similar to that of a logic analyzer including sophisticated event triggering and real time waveform updates.
To make interactive debug even more productive the Eclipse Schematic Logic ProbeTM (SLP) can be used to interactively
view and set logic values directly in the design with a single mouse
click. SLP uses advance place and route algorithms to dynamically
create specialized debug views of the design based on the designer's
probe objectives. SLP removes the need to look at cumbersome paper
schematics in order to debug a design.
'Netlist based constraints' are a
must for interactive debug
Test Engineers familiar with functional test
or functional debug may not be aware of the full capabilities of
IEEE 1149.1 and hence many key architectures of a
robust boundary-scan based test and debug tool. During 1149.1
based debug, ICs can be taken out of their functional state and
controlled in ways that the PCB designer never envisioned.
'Constraint checking' is a term that is used that assures that
an engineer will not inadvertently set conflicting states on
bi-directional or tri-state structures during test development and
design debug. This prevents damage to expensive parts,
especially configured/un-configured FPGAs. ASICs, CPUs or
memory devices. It also prevents unnecessary repairs or delays
in prototype bring-up due to inadvertant 'bus
contentions'. Many low end boundary-scan tools have no
constraint checking at all. Other than Intellitech's Eclipse
all other boundary-scan tools require manual entry of constraints or
manual descriptions of PCB level conditions that need to be checked
to avoid potentially damaging bus contentions. With even a
small PCB design, manual entry of constraints requires hundreds of
entries and requires page by page schematic thoroughness.
Eclipse has constraint checking capabilities
built-in that uses the netlist, net attributes and pin property
information directly from the designer's schematic capture
process. We call this "Netlist based constraints".
At any time, Eclipse is aware of what logic values are being driven
or received on any net, or driver/receiver pin.
Device Configuration and FLASH Programming
Eclipse used in conjunction with the UltraTAPTM test controller enables rapid in-system configuration of all of CPLDs, and FPGAs, using the 1149.1 test infrastructure and industry standard bit files obtained from programmable logic vendors design tools. The bit files contain the required boundary-scan operations needed to configure a device along with the expected responses for each vector. Eclipse compiles the binary data and applies it through the UltraTAP intelligent test controller to configure the FPGA or CPLD on the board. The UltraTAP intelligent test controller has several unique hardware features that significantly reduce configuration times.
Eclipse and UltraTAP also enable efficient in-system FLASH programming. Eclipse unlike other FLASH programming solutions does not require the user to create memory models using C++. The Eclipse Test Development Environment has a standard memory model library as well as several built-in features that simplify the programming process including: Automatic reading/verifying for S-Record, Intel Hex and binary COFF files, the automated handling of program data in complex scan-chains.
Eclipse Test Generation
The Eclipse Virtual Interconnect Test
(VIT) ATPG engine will automatically generate high-coverage, 100%
pin-level fault coverage on boundary-scan nets, test patterns for
IC-to-IC and IC-to Memory interconnect. The Eclipse VIT tests are
generated using robust fault models and will detect and
diagnose to the pin today's common types of manufacturing
structual defects. The VIT engine has three seperate
models for opens, one for nets with two pins, one for nets with 3 or more pins and differential nets as found with SERDES, LVDS, PECL technologies. VIT also models single-ended stuck-at and bridging faults, differential models for bridging and open on LVDS technogies. Complex boundary-scan interconnect with series and termination resistors are also modeled for robust diagnostics to the pin. Included in the test generation process is the automated Shift Path Integrity Test (SPIT). SPIT automatically validates the entire 1149.1 infrastructure of the unit under test (UUT) permitting test engineers to concentrate on the more pressing issue of improving fault coverage.
In the event of a failing test pattern, a test engineer can employ the Eclipse BSID (Intelligent Diagnostic) engine to obtain pin and net-level diagnostics. Diagnostic information
obtained from BSID is used in conjunction with the Virtual Fault AnalyzerTM (VFATM) to produce a visual map of
fault locations on the unit under test.
"We surveyed the three major players in the PC based 1149.1/JTAG test market and after an
objective comparison of the tools, Intellitech's Eclipse Diagnostic System had the “ease-of-use”
features we needed for prototype and production test. The Schematic Logic Probe and Visual Fault Analyzer
provide a design and physical topography necessary for locating and debugging faults.”
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