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Boundary Scan JTAG

scan chain test JTAG ring IDCODE DEVICE ID

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Standard Features:


Base
BSDL Library
Schematic Debug
» Visual Fault Analysis
» Timing Diagram
» TCL Scripting Language

Tests & Programming
Scan Path Test
Interconnect Pin Fault
Memory Test
» FLASH Programming
» FPGA/CPLD ISP
» ScanWorks®


Analog Instrument
VISA Instrument Control
GPIB IEEE 488 Control


Options:
1149.1/1149.6 Interconnect
Interconnect Diagnostics
CircuitMerge
Vector Translator
C++ and Libraries
LabView Interface
Network Licensing

WGL Vector Support
VCS Sim Interface

Hardware Options:


UltraTAP JTAG Controller
PT100Pro Production Tester
PT100 Multiport JTAG
RCT Benchtop Tester
32 bit PCI Card Tester
PC Printer Port
Xilinx PCIII/PCIV
Altera Byteblaster


» Eclipse Brochure

» Eclipse Family Overview
» Test Development
» Manufacturing Test
» Diagnostics and Repair

Boundary Scan Chain Test  - Test Scan Paths

Boundary Scan (JTAG) Chain or "infrastructure test" is performed with the EclipseTM Scan Path Integrity Test (or SPIT). Spit is an automated "vector less" test that verifies that all of a design's test logic is functioning properly. The SPIT creates data and drives it through each configuration of the scan logic before 1149.1/JTAG interconnect tests to assure a fully functioning 1149.1 test infrastructure.

SPIT Simplifies scan chain validation

Today, to meet aggressive product delivery schedules, a design is often brought directly from engineering into full production. This leaves little time to manually develop test suites to validate each configuration of the design's test logic. SPIT will automatically verify all test configurations (sub scan chains, special scan chains, etc.), which will assure a working 1149.1 test infrastructure to begin production test with.

SPIT Overview

The first step is to place the Unit Under Test (UUT) into a known state by resetting the test logic. Applying a Test-Logic-Reset via the Eclipse GUI does this. Next, SPIT runs a Static test, it checks the active scan path length in the database, shifts the appropriate size data vector through the scan chain and displays test results in the Status Window.

SPIT also provides the capability to run a Dynamic test - automatically turns on/off each individual sub chains -- to check the integrity of all secondary scan chain(s) in the design. This is a powerful feature because manually testing each scan configuration in the design can be time consuming and is very prone to human error.

Eclipse will return pin-level diagnostics for each SPIT failure so that the test logic can be debugged, repaired and production test can begin.

scan path test
Eclipse Status Window Displaying Stuck-At 0 Fault During SPIT
- SPIT pinpoints the error between two devices on a board


Eclipse Status Window Displaying Open Fault During SPIT
- SPIT pinpoints a open in device U4's test control logic


Eclipse Status Window Displaying Stuck at Fault on Hierarchial Scan Chain