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Boundary Scan JTAG
1149.1 pcb shorts opens

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Standard Features:


Base
BSDL Library
Schematic Debug
» Visual Fault Analysis
» Timing Diagram
» TCL Scripting Language

Tests & Programming
Scan Path Test
Interconnect Pin Fault
Memory Test
» FLASH Programming
» FPGA/CPLD ISP
» ScanWorks®


Analog Instrument
VISA Instrument Control
GPIB IEEE 488 Control


Options:
1149.1/1149.6 Interconnect
Interconnect Diagnostics
CircuitMerge
Vector Translator
C++ and Libraries
LabView Interface
Network Licensing

WGL Vector Support
VCS Sim Interface

Hardware Options:


UltraTAP JTAG Controller
PT100Pro Production Tester
PT100 Multiport JTAG
RCT Benchtop Tester
32 bit PCI Card Tester
PC Printer Port
Xilinx PCIII/PCIV
Altera Byteblaster


» Eclipse Brochure

» Eclipse Family Overview
» Test Development
» Manufacturing Test
» Diagnostics and Repair

PinFault Diagnostics

The Eclipse Test Development Environment displays in real-time PinFault Diagnostics information in a Status Window when a failure occurs during PCB test. In many cases, standard PinFault Diagnostics provides the user with enough information to resolve failing tests. Advanced Diagnostics for isolating bridging faults and opens can be performed using the optional BSID Diagnostics.

For each failure, PinFault Diagnostics lists the device name and pin where the failure was observed. The Schematic Logic ProbeTM (SLPTM) can be used to examine the states of adjacent nets to aid in fault isolation. The scan bit position where the failure occurred is also displayed in the PinFault Diagnostic Report. This information is helpful when using other Eclipse debug tools such as Timing Diagram Analyzer or the Spreadsheet Viewer.


Eclipse Status Window Displaying Faults on U3 pin P41 and P40